An increasing number of devices including professional and consumer video and audio devices contain circuitry that processes digital signals. The signals that need to be passed between components of these types of systems are often digital rather than analog. Unfortunately, many of these components require signals that have different sample rates. Differences in sample rate can occur even between devices that use the same nominal rate if those devices operate with digital clocks or oscillators that differ in frequency. These differences may vary over time.
In situations where the output signal of one device is intended to be the input signal of another device, it is often necessary to convert the sample rate of the signal so that the two devices can work together. For ease of discussion in this disclosure, the signal whose sample rate must be converted is referred to as the “source signal” and its sample rate is referred to as the “source sample rate.” The desired signal to be obtained by sample-rate conversion is referred to as the “destination signal” and its sample rate is referred to as the “destination sample rate.”
Two ways that are known to convert the sample rate of a digital signal are known as “rational ratio sample-rate conversion” and “asynchronous sample-rate conversion.”
Rational ratio sample-rate conversion can be used when the source sample rate and the destination sample rate are related to one another by a ratio that can be expressed as a constant rational factor. For example, the ratio of the sample rates for signals sampled at 48 kHz and 44.1 kHz can be expressed as the rational factor F=48000/44100=160/147.
Asynchronous sample-rate conversion is a more complex process that can be used when the ratio between the source sample rate and the destination sample rate is not constant. This conversion process must continually assess the ratio between source and destination rates and adapt the conversion process accordingly. This process can be used in situations where the sample rate of either or both signals varies over time.
The remainder of this disclosure is directed primarily to asynchronous sample-rate conversion techniques but principles of the present invention may also be applied to rational ratio sample-rate conversion techniques.
A variety of integrated circuits are available that can convert the sample rate of a digital signal. One example that is suitable for use with audio signals is the SRC4193 chip that is available from Texas Instruments Incorporated, Dallas, Tex. This device is typical of other devices that are available from other manufacturers. It can receive one or two digital signals having sample rates within a wide allowable range and convert the sample rate up or down to provide one or two digital signals having sample rates within a wide allowable range. It has features that are intended to facilitate its use in many practical situations including source and destination sample rates that may vary continuously and may be independent of the chip clock frequency.
The sample rate converter that is implemented in the SRC4193 chip as well as in other known chips use finite impulse response (FIR) filters. In essence, each destination signal sample is generated by applying a low-pass filter to the source signal samples. The cutoff frequency (FC) of the low-pass filter is typically set equal to the lesser of one-half the source sample rate (½ FS,IN) and one-half the destination sample rate (½FS,OUT). This can be expressed as:
      F    C    =      {                                                      F                              S                ,                IN                                      2                                                              when              ⁢                                                          ⁢                              F                                  S                  ,                  IN                                                      <                          F                              S                ,                OUT                                                                                                    F                              S                ,                OUT                                      2                                                              when              ⁢                                                          ⁢                              F                                  S                  ,                  IN                                                      <                          F                              S                ,                OUT                                                        
This type of conversion is often difficult to implement because the cutoff frequency of the low-pass filter is linked to the source sample rate when the sample rate is converted upwards but is linked to the destination sample rate when the sample rate is converted downwards. One implementation uses two low-pass filters. One low-pass filter with a cutoff frequency FC1=½ FS,IN is used to interpolate source signal samples up to a higher intermediate sample rate. The other low-pass filter with a cutoff frequency FC2=½ FS,OUT is used to decimate the intermediate samples down to the destination sample-rate. In the SRC4193 chip, for example, the first low-pass filter interpolates up to a rate that is sixteen times the source sample rate and the second low-pass filter decimates down to the destination sample rate.
In addition to the difficulties explained above, the FIR implementation is not attractive in many applications because it requires a large amount of memory to store filter coefficients. In typical implementations, the FIR filters are used to compute destination signal samples that are delayed by fractions of a sample interval. The amount of the delay must be precise and stable to provide an accurate sample rate conversion and to avoid jitter-related noise in the destination signal. The necessary high time-resolution of the filter can be achieved if a set of filter coefficients for each possible delay is available. A large amount of memory is needed to store all of these coefficients. Alternatively, interpolation can be used with a smaller number of coefficient sets but much memory is still required because FIR filter coefficients generally cannot be determined accurately by interpolation between two sets of coefficients that represent widely-spaced events.